IP you
license.
Chiplets
you commission.
PCIe Gen 6, CXL 3.0, and NoC IP: licensable standalone today. Or engage SignatureIP to design your full Compute, IO, and Memory Expander silicon to spec, assembled from the same blocks.
Every PCIe Gen 6 Subsystem, CXL 3.0 Subsystem, and NoC block in our standalone catalog is also a building block in every Compute, IO, and Memory Expander silicon engagement. License the IP now. Commission the chiplet when you're ready to scale.
verified RTL
Microarchitected for PPA.
Every SignatureIP block is microarchitected from first principles to be modular, reusable, and PPA-optimized.
Low Power
Power domains designed modularly at the microarchitecture level. Active, standby, and retention states built into every IP block. PCIe Gen 6 and CXL 3.0 deliver the low-power implementations on the market.
Optimal Latency · Optimal Throughput
NoC topologies generated by iNoCulator™ are latency-optimal and throughput-optimal by construction.
High Performance
Backward compatible Gen 6 to Gen 1 · 1 GHz operating frequency target on PCIe Gen 6. CHI Rev E.b coherency without latency compromise.
Optimal Area
Modular, reusable microarchitecture eliminates redundancy across IP instances. ATC, ATS, and DTI shared between PCIe Gen 6 and CXL 3.0 subsystems: one NoC attachment point for two protocols.
Standalone IP.
Out of the box.
Four categories. 30+ blocks. and ready to integrate into your SoC today.
ATC, ATS, and DTI are pre-integrated: no separate address translation IP required. The DTI provides an interface to your SoC NoC fabric.
Explore PCIe Gen 6 Subsystem →Shared ATC/ATS/DTI architecture with the PCIe Gen 6 Subsystem: one NoC attachment point handles both PCIe and CXL traffic. CXL Consortium member. CXL 3.0 solution with memory pooling and back-invalidation.
Explore CXL 3.0 Subsystem →- Coherent NoC (C-NOC)
- Non-coherent NoC (NC-NOC)
- IOMMU
- System-level cache (L3 / SLC)
- Proxy cache
- CHI-AXI · CHI-CPI · AXI4-SFI bridges
- PCIe Gen 6 Subsystem ↑
- CXL 3.0 Subsystem ↑
- UCIe D2D interface (partner) (UCIe D2D)
- DMA engine new
- Boot flash controller + DMA new
- eFUSE interface controller (APB)
- PVT sensor interface (APB)
- AXI4-to-APB3 bridge
- Debug interface controller
- SPI master (×4 CS) · SPI slave
- I2C master (×4) · I2C slave
- UART · Watchdog timer
- GP timers · GPIO controller
Your spec.
Our integrated IPs.
One tape-out-ready silicon.
Compute, IO, and Memory Expander silicons are not off-the-shelf products: they're custom design engagements. You bring the architecture requirements. SignatureIP assembles the right IP blocks, integrates them to your spec, and delivers a sign-off-ready silicon.
Start a chiplet design conversation →Bring your spec
We custom design to your spec
Sign-off and deliver
Design your NoC in the browser.
The only cloud-native NoC EDA tool. Set your targets. The tool designs the topology and generates the optimal C-Noc and NC-NOC topology generation. Configures for single-silicon monolithic SoCs and multi-silicon chiplet packages: the same tool serves both design motions.
- ✓Full sign-off flow. RTL feeds directly into Siemens Questa simulation.
- ✓Processor-agnostic. Arm CHI, RISC-V, and custom processor interfaces.
License IP today.
PCIe Gen 6 Subsystem, CXL 3.0 Subsystem, NoC, SysWare, Peripherals: standalone, ready.
Request datasheets →Commission a chiplet.
Compute, IO, Memory, or Transport: custom to your spec, assembled from SigIP blocks. Start the conversation.
Start chiplet design conversation →