Your spec.
Our blocks.
Your silicon.
SignatureIP designs custom Compute Subsystem (CSS) and IO Subsystem (IOSS) chiplets to your specification. Assembled from IP blocks and delivered through a proven design and verification flow from SystemC Model through to Silicon Prototype.
| Dimension | Standalone IP | CSS / IOSS design |
|---|---|---|
| What you get | RTL block + testbench | Complete subsystem RTL |
| Integration work | Your team integrates | SigIP integrates for you |
| Flow coverage | Block-level sign-off | SystemC → Silicon prototype |
| Delivery | Days to weeks | Milestoned engagement |
| IP source | Same SigIP blocks | Same SigIP blocks |
Two subsystems.
Every SoC needs both.
SignatureIP organises its chiplet design engagements around two architectural subsystems: the Compute Subsystem (CSS) and the IO Subsystem (IOSS). These map directly to how SoC architects divide their design space, and to how SignatureIP's IP portfolio is structured.
The CSS is the heart of the chip: the coherent interconnect fabric that ties processor cores, AI accelerators, and on-chip memory controllers into a unified compute plane. SignatureIP designs the full CSS: NoC topology generated by iNoCulator™ from your PPA targets, system-level cache, IOMMU, protocol bridges, and all SoC peripheral and system management IP.
The IOSS connects the SoC to the outside world: high-speed PCIe Gen 6.x and CXL 3.x subsystems with ATC, ATS, and DTI pre-integrated for direct NoC attachment. SignatureIP's IOSS IP is PCI-SIG certified at Gen 5 and provides the PCIe Gen 6.x (32 GT/s non-flit) and CXL 3.x implementations: designed from the ground up without legacy overhead.
Ready to designyour CSS or IOSS?
Tell us which subsystem you're designing, your architecture requirements, and your target timeline. We'll come back with a scope, SystemC exploration results, and a milestone plan.